Comparative Study on Program/Erase E ciency and Retention Properties of 3-D SONOS Flash Memory Cell Array Transistors: Structural Approach from Double-Gate FET and FinFET to Gate-All-Around FET

Comparative Study on Program/Erase E ciency and Retention Properties of 3-D SONOS Flash Memory Cell Array Transistors: Structural Approach from Double-Gate FET and FinFET to Gate-All-Around FET So Ra Park, Kwan Young Kim, Changmin Choi, Kwan-Jae Song, Jun-Hyun Park, Kichan Jeon, Sunyeong Lee, Tae Yoon Kim, Ji Eun Lee, Sangwon Lee, Sungwook Park, Jaeman Jang, Dong Myong Kim and Dae Hwan Kim School of Electrical Engineering, Kookmin University, Seoul 136-702 (Received 20 February 2008) The comparative study on Program/Erase (P/E) e ciency of three-dimensional (3-D) SONOS memory cell transistors is performed by comparing Double Gate (DG), FinFET with Gate All Around (GAA) structures. GAA-CAT is superior to DG-CAT and/or Fin-CAT in terms of all of P/E e ciency, low voltage operation and the integration density. It is shown that this superiority results from the higher FN current in P/E condition (due to the Eeld concentration e ect) rather than the gate controllability in a read operation condition. Furthermore, as DSi decreases, the superiority of GAA-CAT becomes more prominent due to the feature of the Eeld concentration e ect. It is shown that GAA-CAT is very promising candidate for a low voltage P/E e cient ash memory cell transistor. Remaining or further challenging issues will be the body bias control and the scheme for an erasure in block units. In terms of the retention properties, both GAA-CAT and DG-CAT show the superior retention to Fin-CAT due to the corner e ect of Fin-CAT. In the case of Fin-CAT, the maximum Eeld is higher by 1.5 times than that of GAA-CAT and retention characteristic of Fin-CAT is inferior to those of GAA-CAT and DG-CAT by about three orders of magnitude. PACS numbers: 85.30.De, 85.30.Tv